1. Field of Invention
The present invention relates to a thin film transistor, a manufacturing method a thin film transistor, and a circuit and a liquid crystal display device each incorporating the thin film transistor.
2. Description of Related Art
A polycrystalline silicon thin film transistor which can be formed at low processing temperature, i.e., xe2x80x9clow temperature processed polysilicon TFTxe2x80x9d, attracts attention as an element which enables the formation of a high-definition liquid crystal display comprising a large glass substrate containing a driver.
FIG. 38A and FIG. 38B, which is a sectional view taken along line Bxe2x80x94B of FIG. 38A, show, as an example of conventional polysilicon TFT, a top gate type TFT in which a polysilicon thin film which forms source and drain regions is positioned on the lower side, and a gate electrode is positioned on the upper side. This polysilicon TFT is an example of an N-channel TFT.
As shown in FIGS. 38A and 38B, a buffer layer 2 comprising a silicon oxide film is formed on a glass substrate 1, and a polysilicon thin film 3 is formed on the buffer layer 2. Further, a gate insulation film 4 comprising a silicon oxide film is formed to cover the polysilicon thin film 3, and a gate electrode 5 comprising a tantalum nitride film, an aluminum (Al) film or the like is formed. Further, a source region 6 and a drain region 7 into which an N-type impurity is introduced are formed in portions of the polysilicon thin film 3 except at a portion directly below the gate electrode. Also, a layer insulation film 8 comprising a silicon oxide film is formed, contact holes 9 are formed, and a source electrode 10 and a drain electrode 11 are formed.
In the field of general semiconductor devices, in order to achieve a high-speed device, low power consumption, and higher function, miniaturization of devices and utilization of a SOI (Silicon On Insulator) structure have recently attracted attention. In the SOI structure, for example, single crystal silicon layers are formed to hold a silicon oxide film therebetween on the surface of a silicon substrate. However, while the SOI structure has the above advantages it also is influenced by a substrate floating effect because the transistor formation region and the support substrate are electrically isolated. In this case, the problem caused by the substrate floating effect is, for example, deterioration in voltage resistance between the source and drain. This occurs because the holes generated in a high electric field region near the drain region accumulate in a portion below the channel to increase the potential of the channel portion, and thus a parasitic bipolar transistor comprising source, channel and drain regions which serve as an emitter, a base and a collector, respectively, is turned on.
On the other hand, when a polysilicon TFT constructed as shown in FIGS. 38A and 38B is used as a liquid crystal driving element, a signal voltage is applied between the source electrode 10 and the drain electrode 11, and a scanning voltage is applied to the gate electrode 5. However, in this case, the same deterioration in characteristics which occur in the SOI structure due to the substrate floating effect also occurs.
Also, significant deterioration in TFT has been apparent. Since the channel region of TFT is surrounded by an insulation film, a structure is formed in which heat hardly escapes. Therefore, deterioration occurs due to the heat of the TFT itself which is generated during operation. Such deterioration significantly occurs in a TFT having a large channel width.
A polycrystalline silicon TFT exhibits a large leakage current (off current) during an off time and large variations in the amount of current, as compared with a single crystal silicon transistor. This tendency is more significant in low-temperature processed TFTs than TFTs formed by a high temperature process.
For example, as the leakage current (off current) of the TFT of a pixel portion increases, the luminance of a display screen largely varies, and TFT design becomes difficult due to variations in the leakage current (off current).
The present invention solves the above problem.
An object of the present invention is to provide a thin film transistor having a structure in which the leakage current (off current) of the TFT is decreased, and variations in the leakage current (off current) are suppressed, a method of manufacturing a TFT, and a circuit and a liquid crystal display device each incorporating the thin film transistor.
In order to achieve the object, a thin film transistor of the present invention comprises a channel region formed in a non-single crystal silicon thin film on a substrate, first and second regions of a first conduction type formed in the non-single crystal silicon thin film to be separated with the channel region therebetween, and a carrier injection region into which carriers of the conduction type opposite to the first conduction type are generated in a high electric field region near the first or second region flow.
In accordance with the present invention, since the carrier injection region, into which hot carriers generated in the electric field region are flowed, is provided, the amount of the hot carriers flowing into the first or second region is decreased, thereby significantly decreasing deterioration in characteristics, as compared with a conventional thin film transistor.
The thin film transistor of the present invention comprises a channel region formed in a non-single crystal silicon thin film on a substrate, first and second regions of a first conduction type formed in the non-single crystal silicon thin film separated with the channel region therebetween, and at least one third region of the conduction type opposite to the first conduction type which is formed between the first and second region in the non-single crystal silicon thin film.
In the present invention, a plurality of third regions may be formed on the non-single crystal silicon thin film.
The third region may be formed between at least one of the first and second regions and the channel region in the non-single crystal silicon thin film.
The third region may be formed in at least a portion of the channel region.
The first conduction type may be the N type.
The non-single crystal silicon thin film may be a polycrystalline silicon thin film.
The polycrystalline silicon thin film having the channel region, first region and second region may be formed by a low temperature process.
The thin film transistor of the present invention comprises a channel region formed in a non-single crystal silicon thin film on a substrate, and first and second regions of a first conduction type formed in the non-single crystal silicon thin film separated with the channel region therebetween, wherein the width of at least the channel region of the non-single crystal silicon thin film is larger than the minimum width of the first and second regions.
The width of the channel region is preferably 50 xcexcm or more.
The width of the channel region is preferably 100 xcexcm or more.
The thin film transistor of the present invention comprises a plurality of non-single crystal silicon thin films formed to cross a gate electrode on a substrate, a channel region formed in each of the non-single crystal silicon thin films, and first and second regions of a first conduction type formed in the non-single crystal silicon thin film separated by the channel region therebetween, wherein the first and second regions of the plurality of non-single crystal silicon thin films are respectively connected to common electrodes.
The channel width of each of the non-single crystal silicon thin films is preferably 10 xcexcm or less.
The dimension between the outermost sides of the plurality of non-single crystal silicon thin films is preferably 50 xcexcm or more.
The length of the channel region is preferably 4 xcexcm.
The thin film transistor of the present invention comprises a semiconductor thin film island provided on a substrate, source and drain layers formed by selectively introducing an impurity into the semiconductor thin film island, and a gate electrode layer provided opposite to the semiconductor thin film island through an insulation film, wherein at least one of the source layer and the drain layer is formed inside the semiconductor thin film island at a predetermined distance from the outer edge thereof.
Generally, a large leakage current (off current) of a TFT is due to xe2x80x9ccrystal qualityxe2x80x9d. However, as a result of various further studies by the inventors of this application, it was found that the leakage current (off current) of the TFT is significantly affected by xe2x80x9cthe edges of high-concentration source and drain layers which constitute a portion of the outer edge (periphery) of the thin film island, and an electric field between the gate electrode and the thin film islandxe2x80x9d.
The high-concentration source layer and drain layer are provided inside the thin film island to provide a xe2x80x9cspacexe2x80x9d in the outer edge portion, and thus the space relieves the electric field applied to the drain layer. Therefore, a decrease in the leakage current (off current) and suppression of variations thereof are achieved.
A portion of the outer edge of the semiconductor thin film island, which is a region away from the source layer and the drain layer and which overlaps with at least the gate electrode, may comprise an intrinsic layer into which no impurity is introduced.
The xe2x80x9cspacexe2x80x9d described above is defined as the intrinsic layer. In the intrinsic layer, a depletion layer easily extends, and absorbs the electric field. Therefore, the electric field applied to the high-concentration source layer and drain layer is decreased, the leakage current (off current) of TFT is decreased, and current variations are suppressed.
A portion of the outer edge of the semiconductor thin film island, which is a region away from the source layer and the drain layer and which overlaps with at least the gate electrode, may comprise an impurity layer into which an impurity of the conduction type opposite to the source layer and the drain layer is introduced, and an intrinsic layer connected to the impurity layer.
For example, in the case of a NMOS transistor, a portion of the outer edge of the thin film island, which overlaps with at least the gate electrode, has a p layer and an i layer (intrinsic layer). In this case, an electric field relieving effect is obtained, and the leakage current (off current) is decreased, and current variations are suppressed.
The predetermined distance between the outer edge of the semiconductor thin film island to the source or drain is preferably 1 xcexcm to 5 xcexcm.
If the distance between the outer edge of the semiconductor thin film island and the source (drain) is less than 1 xcexcm, processing is difficult. If the distance is over 5 xcexcm, the size of the semiconductor thin film island is consequently increased, and design specifications are not satisfied. Therefore, the distance is preferably 1 xcexcm to 5 xcexcm.
The semiconductor thin film island may comprise polysilicon which is formed by annealing amorphous silicon.
A polysilicon TFT formed by a low temperature process is unable to recover from crystal damage because it is not processed at a high temperature, and the leakage current (off current) of the TFT is liable to increase. Therefore, the present invention can be effectively applied to a polysilicon TFT.
The thin film transistor may have an offset in the relative positional relation between the gate electrode and the drain layer.
The so-called xe2x80x9coffset structurexe2x80x9d has no overlap of the gate and the drain, and is thus effective to decrease the leakage current (off current), while a large offset amount causes a decrease in the on current and an increase in the threshold voltage. Therefore, it is difficult to control the offset amount.
When the present invention is applied to an offset structure MOS transistor, even if the offset amount is not much increased, the leakage current (off current) can effectively be decreased, and current variation are suppressed, thereby facilitating the guarantee of the on current and design.
The thin film transistor may have a dual gate structure in which two gate electrodes are arranged in parallel with each other.
A dual gate structure MOSFET comprises two MOS transistors which are connected in series. In operation the electric field relieving structure of the present invention decreases the leakage current of each MOSFET, and when a rate of reduction (the amount of leakage current after application of the present invention/the amount of leakage current before application) of one MOSFET is xe2x80x9cF ( less than 1)xe2x80x9d, the total rate of reduction in the leakage current of the two MOSFETs is xe2x80x9cFxc3x97Fxe2x80x9d, thereby further decreasing the amount of the leakage current compared to one MOSFET.
The thin film transistor of the present invention comprises a semiconductor thin film island provided on a substrate, a source layer and a drain layer formed by selectively introducing an impurity into the semiconductor thin film island, a first insulation film provided to overlap with only the outer edge of the semiconductor thin film island, a second insulation film formed to cover the surface of the semiconductor thin film island and the first insulation film, and a gate electrode layer provided on the second insulation film.
In the present invention, in order to relieve the electric field between the gate electrode and the source and drain, the first insulation film overlaps the outer edge of the thin film island, and the distance to the edge of the gate is increased by an amount corresponding to the thickness of the first insulation film. As a result, an electric field applied to the source and drain is relieved, the leakage current (off current) of TFT is decreased, and current variations are suppressed.
A circuit in accordance with the present invention comprises the thin film transistor.
The liquid crystal display device in accordance with the present invention is a build-in driver type circuit and comprises the thin film transistor.
The use of the thin film transistor of the present invention decreases the occurrence of operation error in the circuit, and can result in a liquid crystal display device having good image quality.
In the liquid crystal display device, the thin film transistor is preferably used in the circuit portion.
In the liquid crystal display device, the thin film transistor is preferably used as an analog switch means of the circuit portion.
In the liquid crystal display device of the present invention, the thin film transistor is used in the pixel portion.
The leakage current (off current) of the TFT of the pixel portion is decreased, and variations in luminance of the display screen are decreased. Also, variations in the leakage current (off current) of a TFT are suppressed, thereby facilitating design of an active matrix substrate. Therefore, a liquid crystal display device having high performance is realized.
The liquid crystal display device of the present invention comprises the thin film transistor.
When a peripheral circuit such as a liquid crystal driver circuit or the like comprises the TFT of the present invention, a high-performance circuit is realized. The circuit can easily be formed on an active matrix substrate. Therefore, a high-performance liquid crystal display device is realized.
A method of manufacturing the thin film transistor in accordance with the present invention includes forming a channel region in a non-single crystal silicon thin film on a substrate, forming first and second regions of a first conduction type in the non-single crystal silicon thin film separated by the channel region forming, third regions of the conduction type opposite to the first conduction type between the first region and the channel region and between the second region and the channel region, the channel region being of the conduction type opposite to the first conduction type. The method also comprising the silicon thin film forming step of forming a non-single crystal silicon thin film on the substrate, the third region forming step of implanting an impurity ion of the conduction type opposite to the first conduction type into a portion of the non-single crystal silicon thin film to form the third regions, the gate electrode forming step of forming the gate electrode on the third regions of the non-single crystal silicon thin film through a gate insulation film, and the first and second region forming step of forming the first region and second region by implanting an impurity ion of the first conduction type with a dosage smaller than that of ion implantation in the third region forming step.
A method of manufacturing the thin film transistor in accordance with the present invention also includes forming a channel region in a non-single crystal silicon thin film on a substrate, forming first and second regions of a first conduction type in the non-single crystal silicon thin film to be separated with the channel region forming, third regions of the conduction type opposite to the first conduction type between the first region and the channel region and between the second region and the channel region. The method also comprising the silicon thin film forming step of forming the non-single crystal silicon thin film on the substrate, the gate electrode forming step of forming the gate electrode on the non-single crystal silicon thin film through a gate insulation film, the third region forming step of forming the third regions in regions adjacent to the channel region by implanting an impurity ion of the conduction type opposite to the first conduction type using the gate electrode as a mask and a mask material which covers the fist region and second regions, and the first and second region forming step of forming the first region and second region in regions adjacent to the third regions of the non-single crystal silicon thin film by implanting an impurity ion of the first conduction type with a dosage smaller than that of ion implantation in the third region forming step.
The method of manufacturing the thin film transistor in accordance with the present invention includes manufacturing a thin film transistor used for a liquid crystal display device comprising a complementary thin film transistor having both P-type and N-type transistors and comprising a channel region formed in a non-single crystal silicon thin film on a substrate, first and second regions of a first conduction type formed in the non-single crystal silicon thin film separated by the channel region, third regions of the conduction type opposite to the first conduction type which are formed between the first region and the channel region and between the second region and the channel region, the method comprising forming the third regions at the same time as the formation of the first and second regions comprising a transistor of the conduction type opposite to the first conduction type.
The method of manufacturing a thin film transistor in accordance with the present invention comprises, the step of depositing an amorphous silicon thin film, the step of irradiating the amorphous silicon thin film with a laser beam to obtain a crystallized polysilicon thin film, the step of forming a polysilicon island by patterning the polysilicon thin film obtained by laser irradiation, forming a gate insulation film on the polysilicon island and forming a gate electrode on the gate insulation film, the step of forming an insulation layer to cover at least a portion of the outer edge of the polysilicon island, the step of forming a source layer and drain layer by introducing an impurity into the polysilicon island using the gate electrode and the insulation layer as masks, and the step of forming a source electrode and drain electrode.
The source layer and drain layer can be formed inside the outer edge of the thin film island in a self alignment manner using the gate electrode and the insulation layer as masks.